AD9929 |
RFQ for AD9929 Required Field |
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| Technical/Catalog Information | AD9929BBCZ |
| Vendor | Analog Devices Inc |
| Category | Integrated Circuits (ICs) |
| Package / Case | 64-CSPBGA |
| Packaging | Tube |
| Type | CCD Signal Processor |
| Interface | 3-Wire Serial |
| Supply Voltage | 2.7 V ~ 3.6 V |
| Current - Supply | - |
| Input Type | Logic |
| Output Type | Logic |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | AD9929BBCZ AD9929BBCZ |
| Product | Manufacturers | Pack | D/C |
| AD9929 | - | new | - |
The AD9929 is a highly integrated CCD signal processor for digital still camera and digital video camera applications. It includes a complete analog front end with A/D conversion, combined with a full-function, programmable timing generator. The AD9929 also includes horizontal and vertical clock drivers, which allow direct connection to the CCD image sensor.
The AD9929 is specified at pixel rates of up to 36 MHz. The analog front end includes black level clamping, a CDS, a VGA, and a 12-bit A/D converter. The timing generator provides all the necessary CCD clocks: RG-clock, H-clocks, V-clocks, sensor gate pulses, a substrate clock, and a substrate bias pulse. Operation is programmed using a 3-wire serial interface.
The AD9929 is packaged in a 64-lead CSPBGA. It is specified over an operating temperature range of −25°C to +85°C.
Typical Application |
Features |
| Digital still camerasDigital video camcorders | 36 MSPS correlated double sampler (CDS)12-bit 36 MHz A/D converterOn-chip vertical driver for CCD image sensorOn-chip horizontal driver for CCD image sensor6 dB to 40 dB variable gain amplifier (VGA)Black level clamp with variable level controlComplete on-chip timing generatorPrecision Timing core with 0.58 ns resolution2-phase H-clock modes4-phase vertical transfer clocksElectronic and mechanical shutter modesOn-chip sync generator with external sync option64-lead, plastic ball, 9 × 9 grid array Pb-free package |
| Parameter | With Respect To | Min | Max | Unit |
| VDD | VDVSS | VDVSS − 0.3 | VDVSS + 4.0 | V |
| VL | VDVSS | VDVSS − 10.0 | VDVSS + 0.3 | V |
| VH1, VH2 | VDVSS | VL 0.3 | VL + 27.0 | V |
| VM1, VM2 | VDVSS | VL 0.3 | VL + 27.0 | V |
| AVDD | AVSS | −0.3 | +3.9 | V |
| TCVDD | TCVSS | −0.3 | +3.9 | V |
| HVDD | HVSS | −0.3 | +3.9 | V |
| RGVDD | RGVSS | −0.3 | +3.9 | V |
| DVDD | DVSS | −0.3 | +3.9 | V |
| DRVDD | DRVSS | −0.3 | +3.9 | V |
| RG Output | RGVSS | −0.3 | RGVDD + 0.3 | V |
| H1 to H2 Output | HVSS | −0.3 | HVDD + 0.3 | V |
| Digital Outputs | DVSS | −0.3 | DVDD + 0.3 | V |
| Digital Inputs | DVSS | −0.3 | DVDD + 0.3 | V |
| SCK, SL, SDATA | DVSS | −0.3 | DVDD + 0.3 | V |
| REFT, REFB | AVSS | −0.3 | AVDD + 0.3 | V |
| CCDIN | AVSS | −0.3 | AVDD + 0.3 | V |
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; function
